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HD151TS201AT
Mother Board Clock Generator for Intel P4 Chipset Banias and Dothan processor / ODEM and MONTARA-GM chip set
REJ03D0085-0100Z Preliminary Rev.1.00 Oct.21.2003
Description
The HD151TS201AT is Intel CK408 type high-performance, low-skew, low-jitter, PC motherboard Clock generator. It is specifically designed for Intel Pentium(R)4 chipset. Banias and Dothan processor / ODEM and MONTARA-GM chip set
Features
* * * * * * * * * * * 3 differential pairs of current mode control CPU clock 7 PCI clocks and 3 PCIF clocks @3.3V, 33.3MHz typ. 1 copy of 48MHz for USB @3.3V 1 copy of 48MHz for DOT @3.3V 6 copies of 3V66 clock @3.3V,66.6MHz 1 copy of VCH@3.3V, 48MHz Power save and clock stop function. I2CTM serial port programming Programmable Clock Control (Spread Spectrum Percentage, Clock Output Skew, Slew Rate) 56pin TSSOP (244 mils) Ordering Information
Package Type TSSOP-56 pin Package Code Package Abbreviation AT Taping Abbreviation (Quantity) EL (1,000 pcs / Reel)
Part Name HD151TS201ATEL
Note: Please consult the sales office for the above package availability.
Note:
I2C is a trademark of Philips Corporation. Pentium is registered trademark of Intel Corporation
Rev.1.00, Oct.21.2003, page 1 of 28
HD151TS201AT
Key Specifications
* * * * * Supply Voltages: VDD = 3.0 V to 3.475 V CPU Clock cycle to cycle jitter = |150 ps| CPU clock group Skew = 100 ps 3V66 clock group Skew = 250 ps max PCI clock group Skew = 500 ps max
Rev.1.00, Oct.21.2003, page 2 of 28
HD151TS201AT
Pin Arrangement
VDD 1 XIN 2 XOUT 3 GND 4 PCIF0 5 PCIF1 6 PCIF2 7 VDD 8 GND 9 PCI0 10 PCI1 11 PCI2 12 PCI3 13 VDD 14 GND 15 PCI4 16 PCI5 17 PCI6 18 VDD 19 GND 20 66OUT0/3V66_2 21 66OUT1/3V66_3 22 66OUT2/3V66_4 23 66IN/3V66_5 24 PWRDWN# 25 VDDA 26 GNDA 27 VTT_PWRGD# 28
56 REF 55 S1 54 S0 53 CPUSTOP# 52 CPUCLKT0 51 CPUCLKC0 50 VDD 49 CPUCLKT1 48 CPUCLKC1 47 GND 46 VDD 45 CPUCLKT2 44 CPUCLKC2 43 MULT0 42 IREF 41 GND IREG 40 S2 39 USB48 38 DOT48 37 VDD48 36 GND48 35 3V66_1/VCH 34 PCISTOP# 33 3V66_0 32 VDD 31 GND 30 SCLK 29 SDATA
(Top view)
PCISTOP#, MULT0, PWRDWN#, CPUSTOP# = 150K Internal Pull-up
Rev.1.00, Oct.21.2003, page 3 of 28
HD151TS201AT
Block Diagram
3.3 V VDD48 GND48 3.3V VDDA GNDA 7x3.3V VDD 6xGND GNDIREF IREF
XTAL 14.318 MHz OSC
REF(14.318 MHz) 1/m1 CPU PLL 1/n1 SSC Modulator Divide Control Logic Divider CPUCLK[0:2] PCI[0:6] PCIF[0:2] 3V66_0 3V66_1/VCH 3V66[2:4]/66OUT[0:2] (66MHz) 66IN/3V66_5 (IN/OUT) 1/m2 48 MHz USB PLL 1/n2
CPUSTOP# PWRDWN# *MULT0 *S0, 1, 2 SDATA SCLK PCISTOP# VTT_PWRGD#
Divider
USB48 DOT48
Note: Latched Input / Multi Function pin.
Rev.1.00, Oct.21.2003, page 4 of 28
HD151TS201AT
Table1 Clock Frequency Function Table & I2C
Byte8 (bit1, 2, 3, 4, 5)
Bit5 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 Bit4 0 0 0 0 0 0 0 0 Bit3 0 0 0 0 1 1 1 1 Bit2 0 0 1 1 0 0 1 1 Bit1 0 1 0 1 0 1 0 1 CPU 66.67 100 200 133.33 150 166.67 150 166.67 3V66 66.67 66.67 66.67 66.67 50 55.56 66.67 66.67 PCI 33.33 33.33 33.33 33.33 25 27.78 33.33 33.33
Rev.1.00, Oct.21.2003, page 5 of 28
HD151TS201AT
Table2 Hardware Clock Frequency Table (MHz)
S2 0 0 0 0 1 1 1 1 Mid Mid Mid Mid S1 0 0 1 1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 0 1 0 1 CPU 66.67 100 200 133.33 66.67 100 200 133.33 Hi-Z TCLK/2 150 166.67 3V66 66.67 66.67 66.67 66.67 66.67 66.67 66.67 66.67 Hi-Z TCLK/4 50 55.5 66OUT[2:0] 3V66[4:0] 66.67 66.67 66.67 66.67 66IN 66IN 66IN 66IN Hi-Z TCLK/4 50 55.5 66IN 3V66_5 66.67 66.67 66.67 66.67 66IN 66IN 66IN 66IN Hi-Z TCLK/4 50 55.5 PCI 33.33 33.33 33.33 33.33 66MHzIN/2 66MHzIN/2 66MHzIN/2 66MHzIN/2 Hi-Z TCLK/8 25 27.7 Note Un-Buff Mode Un-Buff Mode Un-Buff Mode Un-Buff Mode Buff Mode Buff Mode Buff Mode Buff Mode Tristate Mode Test Mode
Note: TCLK is a test clock over driven on the XIN during test mode.
Table3 CPUCLK Outputs Specification
MULT0 (pin43) 0 1 Board Target Trace/Term Z 50 50 Reference R, Iref = VDD/(3Rr) Rr=221 1% I_REF=5.00mA Rr=475 1% I_REF=2.32mA Output Current Ioh Voh @Z 1.0V @50 0.7V @50
4 x Iref 6 x Iref
Rev.1.00, Oct.21.2003, page 6 of 28
HD151TS201AT
Table4 Clock Power Management Truth Table
Byte0/bit6 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Byte1/bit6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PWRDWN# 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 CPUSTOP# 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 *CPU Stoppable Run Iref*6 Iref*2 Iref*2 Run Hi-Z Hi-Z Hi-Z Run Iref*6 Hi-Z Hi-Z Run Hi-Z Hi-Z Hi-Z *CPU Free Running Run Run Iref*2 Iref*2 Run Run Iref*2 Iref*2 Run Run Hi-Z Hi-Z Run Run Hi-Z Hi-Z
Note: CPUT&C State are controlled by Byte1 (bit3,4,5)
Table5 PCISTOP# I2C control Truth Table
PCISTOP# (pin34) 0 0 1 1 Byte0/bit3 Write bit 0 1 0 1 Byte0/bit3 Read bit (Internal status) 0 0 0 1
Table6 S2 pin Three Level Input
Logic Level 0 (Low) Mid 1 (High) Min Voltage 1.0 V 2.0 V Max Voltage 0.8 V 1.8 V
Rev.1.00, Oct.21.2003, page 7 of 28
HD151TS201AT
I2C Controlled Register Bit Map
Byte0 Control Register
Bit 7 6 5 4 Description Spread spectrum Enable CPUCLK Power down mode setting. See Table4. VCH (pin35) Select 66 MHZ or 48 MHz CPUSTOP# status register Contents "1" = SSC ON "0" = SSC OFF See Table4 "1" = 48 MHz "0" = 66 MHz CPUSTOP# Reflects the current value of external CPUSTOP# (pin53). This bit is read only. Reflects the current value of the internal PCISTOP# function when read. Internally PCISTOP# is a logical AND function of the internal SM Bus registers bit and the external PCISTOP# (pin34). Frequency selects bit2, reflects the value of S2 (pin40). This bit is read only. Frequency selects bit1, reflects the value of S1 (pin55). This bit is read only. Frequency selects bit0, reflects the value of S0 (pin54). This bit is read only. Default 0 0 0 1
3
PCISTOP# Selection. See Table5
1
2 1 0
Reflects the value of the S2 (pin40) Reflects the value of the S1 (pin55) Reflects the value of the S0(pin54)
X X X
Byte1 Control Register
Bit 7 6 5 4 3 2 1 0 Description MULT0 (pin43) Value CPUCLK Power down mode setting. See Table4. Control of CPU2 with CPUSTOP# Control of CPU1 with CPUSTOP# Control of CPU0 with CPUSTOP# CPUT2/C2 Enable register CPUT1/C1 Enable register CPUT0/C0 Enable register Contents MULT0 value. This bit is read only. See Table4 Default X 0
"1" = Free running 0 "0" = Not free running. 0 When this bit is "0", CPUT/C outputs are affected 0 by CPUSTOP# pin. "1" = Enabled "0" = Disabled (CPUT stops "High" & CPUC stops "Low") 1 1 1
Rev.1.00, Oct.21.2003, page 8 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte2 PCI clock enable Register
Bit 7 6 5 4 3 2 1 0 Description (Reserved) PCI6 Enable register PCI5 Enable register PCI4 Enable register PCI3 Enable register PCI2 Enable register PCI1 Enable register PCI0 Enable register "1" = Enabled "0" = Disabled (Each PCI clock stops "Low") Contents Default 0 1 1 1 1 1 1 1
Byte3 PCIF & USB, DOT enable Register
Bit 7 6 5 4 3 2 1 0 Description DOT output enable USB output enable Control of PCIF2 with PCISTOP# Control of PCIF1 with PCISTOP# Control of PCIF0 with PCISTOP# PCIF2 output enable PCIF1 output enable PCIF0 output enable Contents 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) Default 1 1
"1" = Not Free running. 0 When this bit is "1", PCIF outputs are stopped by 0 PCISTOP# pin. 0 "0" = Free running. 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 1 1
Byte4 66OUT, 3V66 Enable Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved 3V66_0 Enable 3V66_1/VCH Enable 3V66_5 Enable 66OUT2/3V66_4 Enable 66OUT1/3V66_3 Enable 66OUT0/3V66_2 Enable 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) 1 = Enable, 0 = Disable (DC Low fixed) Contents Default 0 0 1 1 1 1 1 1
Rev.1.00, Oct.21.2003, page 9 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte5 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved 66IN to 66OUT [2:0] delay bit1 66IN to 66OUT[2:0] delay bit0 DOT Slew Rate Control bit1 DOT Slew Rate Control bit0 USB Slew Rate Control bit1 USB Slew Rate Control bit0 00 = Default 01 = Fast1 10 = Fast2 11 = Slow1 00 = Default 01 = Fast1 10 = Fast2 11 = Slow1 Contents Default 0 0 0 0 0 0 0 0
Byte6 Vendor ID Register
Bit 7 6 5 4 3 2 1 0 Note: This register is read only register. Don't write any data. Vendor ID Register Renesas = "1111" Description Revision Code Contents Default 0 0 0 1 1 1 1 1
Byte7 Byte Count Read Back Register
Bit 7 6 5 4 3 2 1 0 Description Byte Count setting bit7 Byte Count setting bit6 Byte Count setting bit5 Byte Count setting bit4 Byte Count setting bit3 Byte Count setting bit2 Byte Count setting bit1 Byte Count setting bit0 Contents Writing to this register will configure byte. Count and how many bytes will be read back. Default is 17hex = 23 bytes. Default 0 0 0 1 0 1 1 1
Rev.1.00, Oct.21.2003, page 10 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte8 Clock Frequency Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Clock Freq. Control bit2 Clock Freq. Control bit1 Clock Freq. Control bit0 Freq. Select Mode bit 0 = Freq. is selected by latched input S2:0 2 1 = Freq. is selected by I C Byte8 bit5:1 See Table1 Contents Default X X 0 0 0 0 0 0
Byte9 Control Register
Bit 7 6 5 4 3 2 Description Reserved Reserved Reserved Reserved Spread Spectrum Control bit 3V66 & PCI Clock PLL select bit 0 = -0.5% (Default) 1 = -1.0% Contents Default 0 0 0 0 0 0
"0" = CPU PLL "1" = USB PLL When this bit set to "1", 3V66 & PCI clocks will be supply from USB PLL. Not depended on CPU PLL. PLL N Divider Control bit9 PLL N Divider Control bit8
1 0
PLL N Divider Control bit9 PLL N Divider Control bit8
0 0
Note: Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Rev.1.00, Oct.21.2003, page 11 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte10 PLL N Divide Ratio Control Register
Bit 7 6 5 4 3 2 1 0 Description PLL N Divider Control bit7 PLL N Divider Control bit6 PLL N Divider Control bit5 PLL N Divider Control bit4 PLL N Divider Control bit3 PLL N Divider Control bit2 PLL N Divider Control bit1 PLL N Divider Control bit0 Contents PLL N Divider Control bit7 PLL N Divider Control bit6 PLL N Divider Control bit5 PLL N Divider Control bit4 PLL N Divider Control bit3 PLL N Divider Control bit2 PLL N Divider Control bit1 PLL N Divider Control bit0 Default X X X X X X X X
Note: The default N value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value. Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Byte11 PLL M Divide Ratio Control Register
Bit 7 Description N & M divider enable bit Contents 0: N & M value will be determined by S [2:0] or Byte8 bit[5:1]. 1: N & M value will be determined by Byte9,10,11. PLL M Divider Control bit6 PLL M Divider Control bit5 PLL M Divider Control bit4 PLL M Divider Control bit3 PLL M Divider Control bit2 PLL M Divider Control bit1 PLL M Divider Control bit0 Default 0
6 5 4 3 2 1 0
PLL M Divider Control bit6 PLL M Divider Control bit5 PLL M Divider Control bit4 PLL M Divider Control bit3 PLL M Divider Control bit2 PLL M Divider Control bit1 PLL M Divider Control bit0
X X X X X X X
Note: The default M value will be reflected in S [2:0] or Byte8 bit[5:1] frequency setting value. Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.
Rev.1.00, Oct.21.2003, page 12 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte12 Clock Outputs Divider Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Contents Default 0 0 0 0 0 0 0 0
Byte13 Clock Outputs Divider Control Register
Bit 7 6 5 4 3 2 1 0 Description PCISTOP# pin Enable CPUSTOP# pin Enable PWRDWN# pin Enable Reserved Reserved Reserved Reserved Reserved Contents 0 = Enable, 1 = Disable 0 = Enable, 1 = Disable 0 = Enable, 1 = Disable Default 0 0 0 0 0 0 0 0
Note: Byte 12 & 13 must be written together in every case.
Rev.1.00, Oct.21.2003, page 13 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte14 Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved DOT Clock Invert USB clock Invert VCH clock Invert PCI clock Invert 66OUT clock Invert 3V66 clock Invert CPU clock Invert 0=Normal, 1=Inverted 0=Normal, 1=Inverted 0=Normal, 1=Inverted 0=Normal, 1=Inverted 0=Normal, 1=Inverted 0=Normal, 1=Inverted 0=Normal, 1=Inverted Contents Default 0 0 0 0 0 0 0 0
Byte15 Control Register
Bit 7 6 5 4 3 2 1 0 Description REF clock enable Control of PCI6 with PCISTOP# Control of PCI5 with PCISTOP# Control of PCI4 with PCISTOP# Control of PCI3 with PCISTOP# Control of PCI2 with PCISTOP# Control of PCI1 with PCISTOP# Control of PCI0 with PCISTOP# Contents 0 = Enable, 1 = Disable Default 0
0 "0" = Not Free running When this bit is "0", PCI outputs are stopped by 0 PCISTOP# pin. 0 "1" = Free running. 0 0 0 0
Byte16 CPU Skew Control Register
Bit 7 6 5 4 3 2 1 0 Description (Reserved) (Reserved) CPU clock skew controlbit5 CPU clock skew controlbit4 CPU clock skew controlbit3 CPU clock skew controlbit2 CPU clock skew controlbit1 CPU clock skew controlbit0 00 : Delay 0ps 01 : Delay 250ps 0100 : Delay 0ps 0101 : Delay 500ps 0110 : Delay 1000ps 0111 : Delay 1500ps 1000 : Delay 2000ps Don't set 1001 to 1111 10 : Ahead 500ps 11 : Ahead 250ps Contents Default 0 0 0 0 0 0011 : Ahead 500ps 0010 : Ahead 1000ps 0001 : Ahead 1500ps 0000 : Ahead 2000ps 1 0 0
Rev.1.00, Oct.21.2003, page 14 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte17 3V66 Skew Control Register
Bit 7 6 5 4 3 2 1 0 Description (Reserved) (Reserved) 3V66 clock skew controlbit5 3V66 clock skew controlbit4 3V66 clock skew controlbit3 3V66 clock skew controlbit2 3V66 clock skew controlbit1 3V66 clock skew controlbit0 00 : Delay 0ps 01 : Delay 250ps 11 : Ahead 500ps 11 : Ahead 250ps Contents Default 0 0 0 0 0 0 1 0
0100 : Delay 0ps 0101 : Delay 500ps 0011 : Ahead 500ps 0110 : Delay 1000ps 0010 : Ahead 1000ps 0111 : Delay 1500ps 0001 : Ahead 1500ps 1000 : Delay 2000ps 0000 : Ahead 2000ps Don't set 1001 to 1111
Byte18 PCI Skew Control Register 1
Bit 7 6 5 4 3 2 1 0 Description (Reserved) (Reserved) PCI clock skew controlbit5 PCI clock skew controlbit4 PCI clock skew controlbit3 PCI clock skew controlbit2 PCI clock skew controlbit1 PCI clock skew controlbit0 00 : Delay 0ps 01 : Delay 250ps 10 : Ahead 500ps 11 : Ahead 250ps Contents Default 0 0 0 0 0 1 1 0
0100 : Delay 0ps 0101 : Delay 500ps 0011 : Ahead 500ps 0110 : Delay 1000ps 0010 : Ahead 1000ps 0111 : Delay 1500ps 0001 : Ahead 1500ps 1000 : Delay 2000ps 0000 : Ahead 2000ps Don't set 1001 to 1111
Byte19 PCI Skew Control Register 2
Bit 7 6 5 4 3 2 1 0 Description (Reserved) PCI_F2 skew Early or Late PCI_F1 skew Early or Late PCI_F0 skew Early or Late PCI clock skew controlbit3 PCI clock skew controlbit2 PCI clock skew controlbit1 PCI clock skew controlbit0 0100 : Delay 0ps 0101 : Delay 500ps 0011 : Ahead 500ps 0110 : Delay 1000ps 0010 : Ahead 1000ps 0111 : Delay 1500ps 0001 : Ahead 1500ps 1000 : Delay 2000ps 0000 : Ahead 2000ps Don't set 1001 to 1111 "0" = Early "1" = Late Contents Default 0 0 0 0 0 1 0 0
Rev.1.00, Oct.21.2003, page 15 of 28
HD151TS201AT
I2C Controlled Register Bit Map (cont.)
Byte20 PCI Skew Control Register 3
Bit 7 6 5 4 3 2 1 0 Description (Reserved) PCI6 skew Early or Late PCI5 skew Early or Late PCI4 skew Early or Late PCI3 skew Early or Late PCI2 skew Early or Late PCI1 skew Early or Late PCI0 skew Early or Late "0" = Early "1" = Late Contents Default 0 0 0 0 0 0 0 0
Byte21 Slew Rate Control Register
Bit 7 6 5 4 3 2 1 0 Description PCI clock slew rate controlbit1 PCI clock slew rate controlbit0 PCIF clock slew rate controlbit1 PCIF clock slew rate controlbit0 66OUT clock slew rate controlbit1 66OUT clock slew rate controlbit0 3V66 clock slew rate controlbit1 3V66 clock slew rate controlbit0 Contents 00 : Normal 01 : + 00 : Normal 01 : + 00 : Normal 01 : + 00 : Normal 01 : + 10 : ++ 11 : - 10 : ++ 11 : - 10 : ++ 11 : - 10 : ++ 11 : - Default 0 0 0 0 0 0 0 0
Byte22 Slew Rate Control Register
Bit 7 6 5 4 3 2 1 0 Description Reserved Reserved Reserved Reserved REF clock slew rate controlbit1 REF clock slew rate controlbit0 VCH clock slew rate controlbit1 VCH clock slew rate controlbit0 00 : Normal 01 : + 00 : Normal 01 : + 10 : ++ 11 : - 10 : ++ 11 : - Contents Default 1 0 1 1 0 0 0 0
Rev.1.00, Oct.21.2003, page 16 of 28
HD151TS201AT
Absolute Maximum Ratings
Item Supply voltage Input voltage Output voltage *
1
Symbol VDD VI VO IIK IOK IO
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VDD +0.5 -50 -50 50 0.7
Unit V V V mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current Maximum power dissipation at Ta = 55C (in still air) Storage temperature
VI < 0 VO < 0 VO = 0 to VDD
Tstg
-65 to +150
Notes: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
Recommended Operating Conditions
Item Supply voltage Supply voltage DC input signal voltage High level input voltage Low level input voltage Operating temperature VIH VIL Ta Symbol VDD VDDA Min 3.00 3.00 -0.3 2.0 -0.3 0 Typ 3.3 3.3 -- -- -- -- Max 3.465 3.465 VDD+0.3 VDD+0.3 0.8 85 Unit V V V V V C Conditions
Rev.1.00, Oct.21.2003, page 17 of 28
HD151TS201AT
Pin Descriptions
Pin name GND VDD VDDA GNDA CPUT[2:0] CPUC[2:0] CPUSTOP# No. Type Description GND pins Power supplies pins. Nominal 3.3 V. Power supply for PLL core. Power supply for PLL core. "True" clocks of differential pair CPUCLK. These pins are HCSL output. "Complementary" clocks of differential pair CPUCLK. These pins are HCSL output. CPUCLK STOP pin. Active low input. When asserted low, CPUT [2:0] clocks are synchronously disabled in high state and CPUC [2:0] clocks are synchronously disabled in a low state. CPUSTOP# pin is 150 k internal pulled-up. Free running PCI clock 3.3 V output. 33 MHz clocks divided from 3V66. 3.3 V PCI clock outputs. 33 MHz clocks divided from 3V66. PCICLK STOP pin. Active low input. When asserted low, PCI [6:0] clocks are synchronously disabled in low state. This pin does not effect PCIF [2:0] clocks outputs if they are programmed to be PCIF clocks via the device's SM Bus interface. PCISTOP# pin is 150 k internal pulled-up. Frequency selects input. See frequency table2 in page5. Frequency selects input. See frequency table2 in page5. This pin is 3 level input. Qualifying input that latches S [2:0] and MULT0. When this input is at a logic low, the S[2:0] and MULT0 are latched. 4,9,15,20 Ground 31,36,41,47 1,8,14,19 Power 32,37,46,50 26 27 45,49,52 44,48,51 53 Power Power OUTPUT OUTPUT INPUT
PCIF[2:0] PCI[6:0] PCISTOP#
7,6,5
OUTPUT
18,17,16,13 OUTPUT 12,11,10 34 INPUT
S1, S0 S2 VTT_PWRGD#
55,54 40 28
INPUT INPUT INPUT
Rev.1.00, Oct.21.2003, page 18 of 28
HD151TS201AT
Pin Descriptions (cont.)
Pin name REF MULT0 PWRDWN# No. 56 43 25 Type OUTPUT INPUT INPUT Description 14.318MHz reference clock. CPUCLK's output current setting. This pin is 150k internal pull-up. Power down pin. All circuits will be powered down. (Output state of each output is shown in page Table.) Asynchronous active low input pin used to power down the device into low power state. The internal clocks are disabled and VCO and the crystal are stopped. 3.3V 48 MHz USB clock output. 3.3V 48MHz DOT clock output. XTAL input. XTAL output. Don't connect when an external clock is applied to XIN. Data input/output for I2C logic. This pin is internal pull-up to VDD by 150K resistor. Clock input for I2C logic. This pin is internal pull-up to VDD by 150K resistor. A precision resistor is attached to this pin which is connected to internal current reference. A resistor is connected between this pin and GNDIREF. 3.3 V 66 MHz clock. 3.3V clock output selectable with SM Bus byte0, bit5. When Byte0 bit5 is at logic"1", this pin is 48 MHz clock output. When Byte0 bit5 is at logic"0", this pin is 66 MHz clock output. Default is 66 MHz output. If S2 = 1, Input connection for 66OUT [2:0]. If S2 = 0, outputs fixed 66 MHz clock. If S2 = 1, Buffered copies of 66IN. If S2=0, outputs fixed 66MHz clock.
USB48 DOT48 XIN XOUT SDATA SCLK IREF
39 38 2 3 29 30 42
OUTPUT OUTPUT INPUT OUTPUT INPUT/ OUTPUT INPUT IN
3V66_0 3V66_1/VCH
33 35
OUTPUT OUTPUT
66IN/3V66_5 66OUT[2:0]/ 3V66[4:2]
24 23,22,21
IN/OUT OUTPUT
Rev.1.00, Oct.21.2003, page 19 of 28
HD151TS201AT
DC Electrical Characteristics / Serial Input Port
Ta = 0C to 85C, VDD = 3.3 V
Item Input Low Voltage Input High Voltage Input Current Input capacitance Note: Symbol Min VIL VIH II CI 2.0 -50 typ*1 10 Max 0.8 +50 Unit V V A pF VI = 0 V or 3.465 V, VDD = 3.465 V SDATA & SCLK*2 Test Conditions
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions. 2. Target of design, not 100% tested in production.
AC Electrical Characteristics / Serial Input port
Item SCLK Frequency Start Hold Time SCLK Low Time SCLK High Time Data Setup Time Data Hold Time Stop Setup Time BUS Free Time between Stop & Start Condition Symbol FSCLK tSTHD tLOW tHIGH tDSU tDHD tSTSU tSPF Min 4.0 4.7 4.0 250 300 4.0 4.7 Typ Max 100 Unit kHz s s s ns ns s s Test Conditions Normal Mode
Note: Target of design, not 100% tested in production.
Rev.1.00, Oct.21.2003, page 20 of 28
HD151TS201AT
DC Electrical Characteristics CPUT/C Clock
Ta = 0C to 85C
Item Output voltage Output Current Output resistance Note: Symbol VO IO Min 3000 Typ *1 0.695 I(nom) Max 1.2 Unit V mA Test Conditions Rp = 49.9, VDD = 3.3 V VDD = 3.3 V *2 VO = 1.2 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions 2 I(nom) is output current(Ioh) shown in Page5 Table3.
AC Electrical Characteristics CPUT/C Clock (CPU at 0.7V Timing)
Ta = 0C to 85C, VDD = 3.3 V, CL = 2 pF, Rs = 33.2 , Rp = 49.9
Item Cycle to cycle jitter*
1
Symbol tCCS tskS
Min
Typ |150| |100|
Max
Unit ps ps
Test Conditions
CPU Group Skew (CPU clock out to CPU clock out) Rise time Fall time Clock Duty Cycle CPU clock period (66) CPU clock period (100) CPU clock period (133) CPU clock period (200)
tr tf
175 175 45
50
700 700 55
ps ps % ns ns ns ns
VO = 0.175 V to 0.525 V VO = 0.175 V to 0.525 V
15.075 10.25 7.5 4.975
Note: 1.Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 21 of 28
HD151TS201AT
DC Electrical Characteristics / 3V66 Clock (CK408 Type5 Buffer)
Ta = 0C to 85C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / 3V66 Clock
Ta = 0C to 85C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter 3V66 Group Skew Symbol tCCS tskS Min Typ |250| 0 Max 250 Unit ps ps Test Conditions Fig1 Rising edge @1.5 V to 1.5 V Fig.2 0.4V to 2.4V Notes *1
Slew rate Clock Duty Cycle 3V66[5:0] leads 33 MHz PCI Note:
tSL
1.0 45 1.5
50
4.0 55 3.5
V/ns % ns Un-Buffer Mode
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 22 of 28
HD151TS201AT
DC Electrical Characteristics / PCI & PCIF Clock (CK408 Type5 Buffer)
Ta = 0C to 85C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / PCI & PCIF Clock
Ta = 0C to 85C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter PCI Group Skew Symbol tCCS tskS Min Typ |250| 0 Max 500 Unit ps ps Test Conditions Notes Fig1 Rising edge @1.5V to 1.5V Fig.2 *1
Clock Period Slew rate Clock Duty Cycle Note: tSL
1.0 45
20.8316 50 4.0 55
ns V/ns % 0.4 V to 2.4 V
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 23 of 28
HD151TS201AT
DC Electrical Characteristics / USB & VCH Clock (CK408 Type3A Buffer)
Ta = 0C to 85C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 29 Typ *1 Max 50 -29 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / USB & VCH Clock
Ta = 0C to 85C, VDD = 3.3 V, CL = 20 pF
Item Cycle to cycle jitter Clock Period Slew rate Clock Duty Cycle Note: tSL Symbol tCCS Min 1.0 45 Typ |350| 50 Max 2.0 55 Unit ps ns V/ns % 0.4 V to 2.4 V Test Conditions Notes Fig1 *1
20.82985
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 24 of 28
HD151TS201AT
DC Electrical Characteristics / DOT Clock (CK408 Type3B Buffer)
Ta = 0C to 85C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 29 Typ *1 Max 50 -29 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / DOT Clock
Ta = 0C to 85C, VDD = 3.3 V, CL = 10 pF
Item Cycle to cycle jitter Clock Period Slew rate Clock Duty Cycle Note: tSL Symbol tCCS Min 2.0 45 Typ |350| 50 Max 4.0 55 Unit ps ns V/ns % 0.4 V to 2.4 V Test Conditions Notes Fig1 *1
20.82985
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 25 of 28
HD151TS201AT
DC Electrical Characteristics / REF Clock (CK408 Type5 Buffer)
Ta = 0C to 85C, VDD = 3.3 V
Item Output Voltage Symbol VOH VOL Output Current Note: IOH IOL Min 3.1 30 Typ *1 Max 50 -33 Unit V mV mA mA Test Conditions IOH = -1 mA, VDD = 3.3 V IOL = 1 mA, VDD = 3.3 V VOH = 1.0 V VOL = 1.95 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended operating conditions.
AC Electrical Characteristics / REF Clock
Ta = 0C to 85C, VDD = 3.3 V, CL = 30 pF
Item Cycle to cycle jitter Clock Period Slew Rate Clock Duty Cycle Note: Symbol tCCS Min 1.0 45 Typ |1000| 50 Max 4.0 55 Unit ps ns V/ns % Test Conditions Notes Fig1 *1
69.8413
1. Difference of cycle time between two adjoining cycles.
Rev.1.00, Oct.21.2003, page 26 of 28
HD151TS201AT
Clock Out
tcycle n
tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Figure1 Cycle to Cycle Jitter (3.3 V Single Ended Clock Output)
Clock Outx
1.5 V
Clock Outy
1.5 V tskS
Figure2 Output Clock Skew (3.3 V Single Ended Clock Output)
RS = 33.2 CPUT
ZLT = ZLC = 50 LT
TS201 RS = 33.2 CPUC LC
RI(ref) = 475
RP = 49.9
RP = 49.9
CL = 2 pF
CL = 2 pF
Figure3 Load Circuit for CPUT/C
Rev.1.00, Oct.21.2003, page 27 of 28
HD151TS201AT
Package Dimensions
* TSSOP-56
As of January, 2003
14.0 14.2 Max 56 29
Unit: mm
1 *0.19 0.05
0.50 0.08 M
28
6.10
1.0 8.10 0.20 0 - 8 0.50 0.1
0.65 Max
*0.15 0.05
0.10
0.10 0.05
1.20 Max
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-56DAV -- -- 0.23 g
Rev.1.00, Oct.21.2003, page 28 of 28
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